Teksemidesign

Emulation

In the pre-silicon phase, before the silicon is taped out, the latest multimillion complex designs and SOCs require different emulation platforms for firmware qualification, performance tests, and benchmark analysis.

It is simple to verify the intricate test and use case scenarios in the emulation platform, despite the fact that they are challenging and time-consuming in the simulation environment. This helps to lower the verification work and raises confidence levels with regard to benchmark analysis, performance, and latency. Additionally, this reveals RTL and design flaws that are challenging to replicate in an environment for RTL verification.

The Teksemi Design emulation team has completed several projects in the emulation arena with success. At Teksemi Design, we offer our knowledge in a range of up-to-date emulation platforms, including Mentor Graphics Veloce emulation systems, Synopsys Zebu, Palladium from Cadence, and more.

We have extensive experience in

  • Creation of builds for different emulation platforms
  • Pre-silicon design bring up & Device Planning
  • Establishing the flow and setup and test Automation from scratch
  • Setting up different boot flows and code for various industry CPU cores
  • Pre silicon and post silicon bring up.
  • Porting of testcases, Use-case scenarios, Benchmark to next generation and post silicon environment
  • Expertise in the Debug tool chain setup, Coresight and Trace
  • Emulation, Validation & Prototyping on FPGA & Processor-Based Platforms
  • Design Partitioning, Integration, IO & Memory Handling
  • Implementation & Timing Closure
  • Configuration & Hardware Debug

Expertise

Platforms worked for:

  • Processors- ARM, X86, Tensilica, Microblaze, Picoblaze
  • Boards- Altera, Xilinx based multi-FPGA boards
  • Emulators – Zebu, Veloce & Palladium
Tools:
  • Synthesis Tools – Xilinx Vivado, Xilinx ISE, Altera Quartus, Mentor Precision, Cadence Quiclturn
  • Partition Tools – Synopsis Certify
  • Simulation- Modelsim, Questasim, Cadence NCSim & Quickturn
  • System Debug – ARM realview ICE, Xilinx chipscope, Altera signaltap, Synopsis Identify, Debussy, J-Link, Trace-32
Protocols/ IPs:
  • PU cores- ARM, X-86, PowerPC, Tensilica
  • DDR 4 / 3 / 2
  • 0, USB3.0, OTG
  • PCIE 1 / 2 / 3 / 4
  • Ethernet – RGMII, SGMII, QSGMII
  • SATA 1.0/2.0/3.0
  • SDIO
  • MIPI – DSI, MIPI- CSI
  • WLAN 802.11 a/b/p/g
  • H264 Decoders
  • SPI, UART, I2C, I2X, CAN,LIN
  • AXI, AHB, APB
  • PLLs, ADC, LCO, PMU