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Physical Design, STA & DFT

Experienced in block and complete chip development with timing closure, employing industry-standard tools for activities including IR drawing, EM, Low Power Checks, Placement, CTS, Synthesis, and Placement. broad understanding of physical verification techniques such as DRC, LVS, Antenna, and Density in the most recent nodes, such as 14nm, 10nm, 7nm, 5nm, and 3nm.

Physical Design

We provide support throughout RTL to GDSII stages of ASIC development flow. Our experienced team has developed advanced flows for power aware synthesis (UPF, CPF), timing constraint generation (STA), netlist floor planning for best possible PPA and place and route(PNR) for overcoming ever increasing complexity. Our engineer’s in-depth knowledge of EDA tools and scripting skills enable us to deliver full turn-key ASIC development.

Capablities

  • Synthesis
  • Static Timing Analysis
  • DFT
  • Test time reduction
  • Scan compression (XOR, MISR), Logic BIST
  • At speed Memory BIST & repair
  • Constraints and Timing
  • Floor planning
  • Power Grid/ IO and block placement
  • Clock Tree Synthesis
  • ATPG
  • Stuckkat, LOC/LOS, path delay
  • Fault grading
  • Physical Verification (LVS, DRC, ERC)
  • Multi-corner Multi-mode analysis
  • Run Sign-off verification

Expertise

  • Languages and Methodologies: C/C++/System Verilog/Verilog/System C/UVM
  • Protocol Knowledge: High-speed, ARM-based, Memory, Storage, Serial IO, MIPI
  • Processor Expertise: ARM, MIPS, x86, Power
  • Low Power Verification – UPF Power-aware RTL and Gate Simulation
  • Formal/Static Property based Verification

STA (Static Timing Analysis)

STA (Static Timing Analysis) is one of the most important area in Semiconductor chip Designing. Having an in-depth knowledge and exposure in STA provides opportunity in exploring and understanding how other domains operate to design chip. As expert say Timing and Performance is almost everything, STA turns out to be the single most important domain which collaborates with every other areas of chip designing.

Expertise

  • Process Variation and related Margins
  • Peripheral Interface protocols and timing
  • IR aware timing and Timing aware IR
  • Mission mode and Testmode Constraints (Data flow)
  • High Speed Clocking Architecture
  • Synchronous/Asynchronous Circuit designs
  • Signal Integrity
  • PLY (Parametric Limited Yield) and DLY (Defect Limited Yield) yield analysis of new technology nodes (Test Chips)